1) Field of the Invention
The preferred embodiments of the invention relate generally to fabrication of semiconductor devices and more particularly to the fabrication of a device with sidewall spacers and more particularly to a method for forming sidewall spacers for a gate structure.
2) Description of the Prior Art
As the physical geometry of semiconductors continues to shrink, the space between gate electrodes shrinks as well. As design rules shrink, it is important to reduce the size of the elements for transistors.
One approach which has been used to solve this problem is the use of spacers on the gate electrode sidewalls which are smaller at the top than they are at the bottom, such as L-shaped spacers. In a typical L-shaped spacer two dielectric layers (the first composed of silicon nitride and the second composed of silicon oxide) are formed over and around a gate electrode, then anisotropically etched. However, the top oxide portion of the spacer can not be easily removed without damaging oxide isolation structures. Conversely, if the top oxide portion of the spacer remains, it can be affected by post-etch wet chemical process causing inconsistent spacer shape and size across the IC and between IC""s. Furthermore, furnace based LPCVD SiO2/SiN film stacks are formed at high temperatures and are relatively difficult to control spacer widths.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents. U.S. Pat. No. 6,380,039B2(Badenes et al.) shows a process for an L-shaped spacer.
U.S. Pat. No. 6,294,480b1(Pradeep et al.) and U.S. Pat. No. 6,346,468b1(Pradeep et al.) show other processes for spacers.
U.S. Pat. No. 6,277,683b1(Pardeep et al.) reveals another process for an L-shaped spacer.
U.S. Pat. No. 6,348,386b1(Gilmer) shows a process for a gate dielectric layer.
U.S. Pat. No. 6,297,539b1(Ma et al.) discloses a gate dielectric layer processes.
It is an object of an embodiment of the present invention to provide a method for fabricating spacers in a semiconductor device.
It is an object of an embodiment of the present invention to provide a method for fabricating L-shaped spacers using atomic layer deposition (ALD) processes in a semiconductor device.
An embodiment of the present invention provides a method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed.
In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD).
In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) processes. The second and third dielectric layers preferably have different etch characteristics to that the third dielectric layer can be etched selectively to the second dielectric layer.
The embodiments preferably use atomic layer deposition (ALD) processes to form spacers, as ALD processes can grow films with precise thickness control. This is an advantage because the width of the spacer will after the source/drain extension series resistance and hence the drive current.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.